Custom sound chip

StinkerB06

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Sep 24, 2019
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Who wants to develop a custom sound chip for the CX16? The VERA chip is already FPGA-based, so why not an FPGA sound chip to go along with it? Maybe with C64 SID compatibility?

The VERA Programmer's Reference says that the $F6000 - $F6xxx memory region is dedicated to audio. Is the sound hardware planned to be part of the VERA chip?
 

BruceMcF

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May 19, 2019
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Who wants to develop a custom sound chip for the CX16? The VERA chip is already FPGA-based, so why not an FPGA sound chip to go along with it? Maybe with C64 SID compatibility?

The VERA Programmer's Reference says that the $F6000 - $F6xxx memory region is dedicated to audio. Is the sound hardware planned to be part of the VERA chip?
They are presently looking at two chiptunes chips and two stereo DAC channels. I presume the Vera registers include the stereo DAC once they lost the 8bit parallel IO ports when the AY3 chips didn't work. I also presume that how it will work it still being worked on, which is why it is $F600 - $F6xx without a specific ending address.
 

StinkerB06

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Sep 24, 2019
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They are presently looking at two chiptunes chips and two stereo DAC channels. I presume the Vera registers include the stereo DAC once they lost the 8bit parallel IO ports when the AY3 chips didn't work. I also presume that how it will work it still being worked on, which is why it is $F600 - $F6xx without a specific ending address.
I've seen that they're planning on using the YM2151 and SAA1099. The YM chip was tested and working, and is a part of the official CX16 emulator. When will progress begin on implementing the SAA chip?
 

BruceMcF

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I've seen that they're planning on using the YM2151 and SAA1099. The YM chip was tested and working, and is a part of the official CX16 emulator. When will progress begin on implementing the SAA chip?
I don't have any inside information, just what some member of the design team happens to share on FB. We tend to hear about progress they have made, not the current state of play.

But I assume that if they have the YM chip tested on the bus, the progress on integrating the SAA chip is the next thing they are tackling ... it seems like the last piece to nail down other than the final feature set of Vera.
 

GregZone

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Sep 29, 2019
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I'm not up-to-speed with ealier sound discussion, but I have noted the later discussion on the original prototype board AY-3-8910 chips not being fast enough, and that YM2151 chips are looking like the likely choice.

What I don't understand is that given there are already completed FPGA cores available (GPL) for both the AY-3-8910 and the YM2151 sound devices, why would you not use these to make the VERA FPGA both the Video & Sound controller?

This approach would not only save on extra chip count, but it would also lower the overall BOM cost, simplify the PCB design / layout, and take the design 1 step closer to David's "Stage 3" lowest cost all FPGA core based smallest PCB solution.
 
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jdifelici

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Stage 1 is supposed to be all single chips so anyone can pick a chip, see how it is integrated into the system, and try and understand it -- also, remember that David is targeting this for educational purposes as well. So anything they can put "outside" of the FPGA is good for this purpose, and they are only using an FPGA because there is no stand alone graphic chip they they liked that is still in production -- if they could have found a suitable graphics chip, there would be no FPGA. Now stage 3 may all end up on an FPGA for cost and form factor, but that stage serves a different purpose. Looking at a stage 3 board with an FPGA and maybe one or two more chips, you would have no clue as to what it does and it would be a lot harder to follow -- or you would be looking at Verilog which it a different beast then looking at chips and a schematic.
 

BruceMcF

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I'm not up-to-speed with ealier sound discussion, but I have noted the later discussion on the original prototype board AY-3-8910 chips not being fast enough, and that YM2151 chips are looking like the likely choice.

What I don't understand is that given there are already completed FPGA cores available (GPL) for both the AY-3-8910 and the YM2151 sound devices, why would you not use these to make the VERA FPGA both the Video & Sound controller?

This approach would not only save on extra chip count, but it would also lower the overall BOM cost, simplify the PCB design / layout, and take the design 1 step closer to David's "Stage 3" lowest cost all FPGA core based smallest PCB solution.
The stage 1 board would be ALL ASIC if there was a suitable video chip on the market, so in the Stage 1 board, Vera is supposed to be only filling in the gap for ASIC that is NOT available (which also turned out to be 65xx bus compatible UART, once it turned out that the WDC ACIA is buggy). That is the design target for the reference design.

If a better FPGA can integerate whatever features the Vera ends up with along with solid models of the YM2151 and the tone generator chip they are using (they aren't using AY3's anymore because the actual AY3's don't work with their selection and address bus timings), ...
... well, who knows, mayby they MIGHT integrate one or both of them together in the Stage 2 board (especially since the YM2151 is just "large stock in inventory" rather than in current production). But first they are getting the reference design, based on as much ASIC as feasible.

So now they are working on integrating real sound chips into addresses generated by a real CPU and device selection generated mostly by glue logic (all under a system clock driven by their FPGA). If that works, that is the reference design. And since that is harder than making all of that work in FPGA, if it works in the reference design, cost engineering should not result in big "gotchas".
 
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BruceMcF

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I just saw the new VERA 0.9 documentation, looks like they scrapped the SAA's for a new 16-channel PSG!
Not clear that they scrapped them ... the Vera developer says the PSG was part of his plans from the outset, so they've at least been on the drawing board even before the AY3's were abandoned in favor of the OPL/SAA combo.

If they are easy enough to write Basic sound routines for, it might happen, but there's intrinsically a lot more knowledge extant on how to program for the SAA's than for these new PSG's.
 

grommile

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Nov 24, 2019
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The PSGs on the Vera look dead simple to code for.

Quite limited compared to some sound chips, admittedly – there's no envelope control, no modulation, and no filtering – but still, dead simple.
 
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StinkerB06

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Sep 24, 2019
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The PSGs on the Vera look dead simple to code for.

Quite limited compared to some sound chips, admittedly – there's no envelope control, no modulation, and no filtering – but still, dead simple.
I agree. David wants the CX16 to be as easy to program. As such, it has a simple chip for making tones or noise, and a more-complicated chip for those who want it.
 

PowerfulBadBoy

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Jul 17, 2019
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Sounds pretty good! The previous contenders were a bit too square wave focused (Although the SAA chip could actually do triangle but for some reason nobody uses it).

Personally if I were designing a soundchip I'd clone the SCC (Just imagine how much memory those samples would take up though!!!) but this is a Commodore inspired project and who doesn't love a bit of SID? I've never used the modulation or filters so I don't know what I'm missing. 16 channels is rad and it means you get enough for good music AND sound effects! (SO MANY chips miss this one!)

E: Also, I tepidly await seeing this combined with the Yamaha chip.
So many megadrive games used their SN76489 (Basically a clone of the AY-3-890) alongside their far more powerful YM2616 for great effect. I was personally never a fan of the AY-3-890 on it's own but it's "sorrowful" sound works very well when combined with a more powerful synth!
I wonder what goodies THIS combination will have in store!
 
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StinkerB06

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Sounds pretty good! The previous contenders were a bit too square wave focused (Although the SAA chip could actually do triangle but for some reason nobody uses it).
The SAA can also do sawtooth as well. That and the triangle waveform are generated by its envelope generators, which significantly reduces polyphony but allows composers to at least not get bored by square waves or noise.

E: Also, I tepidly await seeing this combined with the Yamaha chip.
So many megadrive games used their SN76489 (Basically a clone of the AY-3-890) alongside their far more powerful YM2616 for great effect. I was personally never a fan of the AY-3-890 on it's own but it's "sorrowful" sound works very well when combined with a more powerful synth!
I wonder what goodies THIS combination will have in store!
You mean AY-3-8910 and YM2612? Also, the SN is fundamentally incompatible with the AY, as its interface and channels are quite different.

I'd too want to hear 25-channel tunes on this thing, once SKKTracker is in a usable state. I could easily predict how multi-chip 0CC-FamiTracker modules like this one could sound on the crazy YM2151+PSG+PCM setup they have right now.
 
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tepigu

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Dec 2, 2019
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Native tracker developer here.

From the recent board design reveal. I think it's time to move YM2151+SAA1099 out as an expansion card just like the SAAYM card. The problem is that right now there's too many sound channels for the base system and those chips are not in main production (which conflicts with what David originally wanted). VERA PSG itself already offers enough sound capabilities than any 8-bit systems of the era. Having too many sound channels will just waste more memory and update time for sound engines which is critical in games and demos.

To be honest, I don't like the development process of this system at all since they never freeze the specification. Next day they will move the registers around, next day they will add something new that's never documented. It's like they don't know how to properly manage the project development and actually understand the design goal. To quote from David: "And at some point I just started to feel like this project has allowed a feature creep to spiral out of control and it really no longer resembles the system I originally wanted."
 

BruceMcF

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May 19, 2019
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Native tracker developer here.

From the recent board design reveal. I think it's time to move YM2151+SAA1099 out as an expansion card just like the SAAYM card. The problem is that right now there's too many sound channels for the base system and those chips are not in main production (which conflicts with what David originally wanted). VERA PSG itself already offers enough sound capabilities than any 8-bit systems of the era. Having too many sound channels will just waste more memory and update time for sound engines which is critical in games and demos.

To be honest, I don't like the development process of this system at all since they never freeze the specification. Next day they will move the registers around, next day they will add something new that's never documented.
Really, the way to cope with not liking how things work before the specification is frozen is to set it to one side until the specification is frozen, then come back to it.

It's like they don't know how to properly manage the project development and actually understand the design goal. To quote from David: "And at some point I just started to feel like this project has allowed a feature creep to spiral out of control and it really no longer resembles the system I originally wanted."
Except you are reacting to what is quite clear NOT feature creep. The guy that is working on Vera has said that the PSG and PCM channels were are part of the design goal from the outset. The YM2151 and SAA1099 have been part of the design since the AY3's were abandoned.

If you want to develop a tracker that only targets the resources on the Vera, go for it. Certainly other projects that adopt the Vera design will be happy to have the logic for that sorted out, even if they won't all necessarily have a 65c02 CPU.
 

tepigu

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Dec 2, 2019
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Sorry, I was quite upset the other day. You do have a point that I'm too early into the specifications to do anything big for it. Maybe I'll just wait until everything is settled down. I have other more important projects to do anyway.
 
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May 22, 2019
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Yes, same here. I don't necessarily need hardware in hand, but I want to see the engineering design frozen so we can get a final software design. Stuff I wrote last last year simply doesn't work any more, and there's still no reliable disk I/O.

I can wait. In the meantime, I'm playing with my Tandy 102 and 200 computers. =)
 
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