It is planned to be based on one of the existing 65c832 cores already available, though thoroughly enhanced.
The COP instruction will be replaced to be a vectored jump table with 256 vectors that intelligently know where they are jumping and sets the processor mode (8 16 32) and return to the mode it was in when it exits the routine.
This will allow for fast trampolining between modes and easily be able to call 8 bit code from 32 bit and vice versa.
It will also allow for minimal 8 bit ROM (since you can easily trampoline in and out), right now only 2kb of 8 bit kernel is planned, and 2k of IO in the first 64k, mostly trampolines to 16 bit space. This maximizes the RAM you can use in 6502 mode.
The WDM instruction will also be fully utilized, mostly for 32 bit instructions that can be used in any mode, so even if you are in 8 bit mode you can still touch every RAM address.. In general, if you want to use an instruction in 32 bit form, instead of lda #$80,x, you would do lda.l or lda.32 #$80,x. They do the same thing in 32 bit mode but the latter will always execute 32 bit in any mode (and will compile as it's 8 or 16 bit equivalent but with a $42 prefix).
OK back again.. I want to go over the planned hardware capabilities thus far, which I believe are fully reachable with the MiSTer FPGA or dedicated FPGA/ASIC mainboard config (which would in theory have all sorts of expansion options, from C64 expansions to PCIe devices (tho only if it reaches more than an FPGA implementation)..
The 65x832 (Expanded 65832) will not have multiplexed lines, as there is no real reason to try to stick it into a 65816 slot. If a hardware implementation to put one in a slot is desired, i'd rather have adaptive circuitry to do the multiplexing.
Instead there will be 32 real address and data lines, and 4x byte enables.
Expect this to have cycle exactness for 6502 mode only. 65816 and 65832 instructions will be optimized to execute "as fast as possible".
Expected speeds are 33mhz (for 133mhz rated chip ram) or 40mhz (for 160mhz rated chip ram). with lower compatibility speed modes.
The coprocessor line will still exist, but the instruction to invoke it will now be 42 02 xx (COP $xx), 42 xx Will be for vector jumps but have not decided what to call it yet, probably SVC $xx.
A partially functional MMU can protect memory pages (in 256 byte blocks) by treating them as ROM (ignore write), throwing an interrupt, or loading a block off disk and mapping it to a DDR3 location.
Multitasking and fast context switches will be implemented though the plan for that is not complete yet.
A VIX chip (Video Interface Expansion) for handling all modes, currently planned max resolution is 1280x720 with RGBA color, but this could become larger with more RAM expansion options.
It will also feature 256 sprites of arbitrary size (the whole screen if desired) which can also be used as parallax planes, the only limit is the amount of chip RAM available (standard size is 32m minus what is used by OS, programs, etc)
A SID extreme chip featuring 9 voices, 3 center/mono, 3 left, and 3 right. A compatibility memory map will allow you to use the center channels just like a regular 6581. It has your standard SID waveforms and ADSR, and all SID channels also have a 'sampled waveform' setting which will play back up to 64KB of raw PCM data at a time, and can be directed to play more by setting a continuation register. It also lets you record samples in a raw PCM format.
Options for emulating devices by trapping exceptions in the I/O area is available.
Hard disks, SSDs, and flash media of sizes up to 256TB will be supported. TRIM will be supported by the hardware.
Floppies with up 2 heads, 128 sectors and 256 tracks are supported. Sector sizes of 64KB are supported.
Theres much more, if you read the memory map, it changes often as I plan, so hit refresh once in a while.
i don't think its that much more complex than an Acorn Archimedes or an AGA Amiga. Somewhat more than an SNES though. It can be done on a MiSTer for sure. Alot of the new instructions for the CPU are the same as for the existing 65832 cores, just with an automatic promotion to a 32 bit mode.
That being said, if it does get too complex, theres a host of things that I can leave out (in fact the PCI/Zorro stuff is more of a plan for if it becomes an independant board, they can't be done on the FPGA. Perhaps I need a list of "definitely doable" stuff. The 6502, VIX, SID Extreme and MMU are all doable. And for I/O. well much of that stuff is supported by the ARM core on the MiSTer, so if it became a production board, it'd probably get a $5 tablet chip from China with 4 ARM cores and stuff..