Parallax Propeller 2


New Member
Sep 25, 2019
Hi, just starting this topic here in case hardware lovers/hackers haven't been following Parallax. Their new Propeller 2 chip might be of interest to those who want to DIY a complete system and can loosen up their strict 8-bit love. You get a lot of easy IO and interfacing but it's a very different school of thought than the Arduino and other microcontroller/SBC camps. ADC/DAC, VGA, USB, SD, and a crap ton more are within a programmer's reach, without adding any or many support chips. See pasted overview below.

The forums over there are active and generous with help, including Chip Gracey. Yes, the chip designer's name is Chip. :unsure:

A Propeller 2 chip has 8 cores, called "cogs". It can be clocked from kHz into hundreds of MHz, or stopped completely. The current eval board runs at 180 MHz, overclockable to 300 MHz but you can also drop into kHz or stop it completely for power saving. There are 64 IO pins. Each cog has:

  • Access to all I/O pins, plus four fast DAC output channels and four fast ADC input channels
  • 512 longs of dual-port register RAM for code and fast variables
  • 512 longs of dual-port lookup RAM for code, streamer lookup, and variables
  • Ability to execute code directly from register RAM, lookup RAM, and hub RAM
  • ~350 unique instructions for math, logic, timing, and control operations
  • 2-clock execution for all math and logic instructions, including 16 x 16 multiply
  • 6-clock custom-bytecode executor for interpreted languages
  • Ability to stream hub RAM and/or lookup RAM to DACs and pins or HDMI modulator
  • Ability to stream pins and/or ADCs to hub RAM
  • Live colorspace conversion using a 3 x 3 matrix with 8-bit signed/unsigned coefficients
  • Pixel blending instructions for 8:8:8:8 data
  • 16 unique event trackers that can be polled and waited upon
  • 3 prioritized interrupts that trigger on selectable events
  • Hidden debug interrupt for single-stepping, breakpoint, and polling

The hub provides the cogs with:

  • Up to 1 MB of contiguous RAM in a 20-bit address space (P2X8C4M64P contains 512 KB)
  • 32-bits-per-clock sequential read/write for all cogs, simultaneously
  • readable and writable as bytes, words, or longs in little-endian format
  • last 16KB of RAM also appears at the end of the 1MB map and is write-protectable
  • 32-bit, pipelined CORDIC solver with scale-factor correction
  • 32-bit x 32-bit unsigned multiply with 64-bit result
  • 64-bit / 32-bit unsigned divide with 32-bit quotient and 32-bit remainder
  • 64-bit → 32-bit square root
  • Rotate (X32,Y32) by Theta32 → (X32,Y32)
  • (Rho32,Theta32) → (X32,Y32) polar-to-cartesian
  • (X32,Y32) → (Rho32,Theta32) cartesian-to-polar
  • 32 → 5.27 unsigned-to-logarithm
  • 5.27 → 32 logarithm-to-unsigned
  • Cogs can start CORDIC operations every 1/2/4/8/16 (#cogs) clocks and get results 55 clocks later
  • 16 semaphore bits with atomic read-modify-write operations
  • 64-bit free-running counter which increments every clock, cleared on reset
  • High-quality pseudo-random number generator (Xoroshiro128**), true-random seeded at start-up, updates every clock, provides unique data to each cog and pin
  • Mechanisms for starting, polling, and stopping cogs
  • 16KB boot ROM
  • Loads into last 16 KB of hub RAM on boot-up
  • SPI loader for automatic startup from 8-pin flash or SD card
  • Serial loader for startup from host
  • Hex and Base64 download protocols
  • Terminal monitor invocable via "> " (greater than followed by a space) and then CTRL+D
  • TAQOZ Forth invocable via "> " (greater than followed by a space) and then ESC

Each smart I/O pin has the following functions:

  • 8-bit, 120-ohm (3ns) and 1k-ohm DACs with 16-bit oversampling, noise, and high/low digital modes
  • Delta-sigma ADC with 5 ranges, 2 sources, and VIO/GIO calibration
  • Several ADC sampling modes: automatic 2n SINC2, adjustable SINC2/SINC3, oscilloscope
  • Logic, Schmitt, pin-to-pin-comparator, and 8-bit-level-comparator input modes
  • 2/3/5/8-bit-unanimous input filtering with selectable sample rate
  • Incorporation of inputs from relative pins, -3 to +3
  • Negative or positive local feedback, with or without clocking
  • Separate drive modes for high and low output: logic / 1.5 k / 15 k / 150 k / 1 mA / 100 µA / 10 µA / float
  • Programmable 32-bit clock output, transition output, NCO/duty output
  • Triangle/sawtooth/SMPS PWM output, 16-bit frame with 16-bit prescaler
  • Quadrature decoding with 32-bit counter, both position and velocity modes
  • 16 different 32-bit measurements involving one or two signals
  • USB full-speed and low-speed (via odd/even pin pairs)
  • Synchronous serial transmit and receive, 1 to 32 bits, up to clock/2 baud rate
  • Asynchronous serial transmit and receive, 1 to 32 bits, up to clock/3 baud rate